HHIGH CIRCUITS : MEMORY TECHNOLOGY
Design Innovations for radical PPA gains
HHIGH CIRCUITS : What we Offer
Hhigh Circuits : An Intellectual Property (IP) company based in Bangalore (India)
Offering Architectural and Circuit innovations in Memory Technology for radical PPA gains
- Innovative circuit design techniques used in Periphery logic using Foundry bit cell or customer provided bit cell
Technology consisting of portfolio of patented innovations built by an industry experienced team
Offering Technology addressing complete portfolio of Embedded On-Chip Memories
- SRAM
- Multi-Port Register File
- TCAM
- ROM
On-chip Memories
Low Power Memories targeting markets such as – AI, ML, Mobile, Automotive, IoT etc.
- 50% Lower Power ULP compilers
- ULV and Sub-threshold compilers
- ULL Compiler
High Perf Memories targeting markets such as CPU, GPU, HPC, Networking etc.
- 2x High Performance UHS compilers
- 1R1W 6R6W Multiport RF compilers
MEMORIES are Everywhere
- PPA driven by process node scaling: companies keep moving to latest nodes to get PPA advantage
- Hhigh Circuits offers architecture innovations for radical PPA gains over or on top of process node scaling
HHIGH CIRCUITS Memory Offering
Patented Architecture / Circuit design techniques addressing entire Memory Portfolio – SRAM, Multiport Register File, TCAM, ROM
Innovations are agnostic to Foundry, Process Node, Transistor Technology – Bulk-CMOS, FD-SOI, FinFET, GAA etc.
Using Foundry Bit Cell / Customer provided Bit Cell & no change in Assist circuits
Low Power Memories
- Up to 50% Lower Power SRAM
- Extendable to other Memories : RF, ROM
- No Impact on Timing
- Area Impact (3 to 7%) – Area-vs-Power tradeoff graph
- Power Saving % will depend on the instance size
- Higher power saving for Larger instances
- 50% Lower Search Power TCAM
- Timing & Area impact – about 5%
High Performance Memories
- 2x Higher CLK Frequency (UHS)
- OR
- 2x No of ports (Multiport) with considerably Lower Power (30 to 40%) & Area (40 to 60%)
- Addressing RF, TCAM & ROM
- Power / MHz – Remains same
- Area impact – < 5%
- Current Estimates given within the framework of regular support Foundry offers to Tier-1 Fabless Semi Companies
- PPA can be optimized further with support from Foundry design team
- ZERO to minimal Area Impact – A Layout technique optimizing Halo Cell Region can be mutually explored
- Support Cells such Edge Cells, Strap Cells etc., get used in some of the techniques and optimized versions of these cells can help in efficient implementation
50% Low Power / 2x Performance for ZERO to minimal impact on Area
HHIGH CIRCUITS Memory : Easy to Adapt
- Periphery Logic of the Memory built using the innovative technology
- Bit Cell remains untouched
- It is seamless to the accessing Logic and interface to the Memory
- Using Foundry Bit Cell & no change in Assist circuits
- No RTL change
- No Changes to the legacy proven circuits
- Sense-amp, Self-timed, Tracking, Read/Write Assist etc.
- Memory design practices retained
- Limitation of max allowed RPB, boundary rules and MET layers usage adhered to
- Proven practices followed on key design aspects like - target vdiff, internal tsu/thd margins, contention and floating states, variation, noise and reliability etc.
- Seamless operations at Low VDD
- No impact on Yield
Standard Memory built using the Foundry Bit Cell
- We can optimize the periphery logic while the Bit Cell remains untouched
Custom Bit Cell Provided by the customer
- Due to confidentiality reasons, customers may not want to share the Bit Cell Design
- We can optimize the Periphery logic with the RC Model of the Bit Cell
- Tested in Latest Multi-Vt Finfet process node while all OCV, Process variation, EMIR and Reliability effects accounted for
Memory Solutions for AIML & IoT
ULP and ULL SRAM < 1Mb
| Competition | Hhigh Circuits | |
|---|---|---|
| AREA | 1x | 1x |
| ACTIVE PWR | 1x | 0.7x - 0.5x |
| LKG PWR | 1x | 0.7x - 0.5x |
| PERFORMANCE | 1x | 1x |
Note: Large-range SRAMs are reqd. to implement L2 and L3 Caches and to store on-chip Input and Filter data in AIML. Both active and leakage power are critical
0.5v-0.4v ULV SRAM < 512Kb
| Competition | Hhigh Circuits | |
|---|---|---|
| AREA | 1x | 1x |
| ACTIVE PWR | 1x | 0.5x |
| LKG PWR | 1x | 0.5x |
| PERFORMANCE | 1x | 1x |
Note: ULV SRAMs are required for AIML and IoT applications to improve energy efficiency drastically
Small-range Single and Two Port RF < 16Kb
| Competition | Hhigh Circuits | |
|---|---|---|
| Array Efficiency | 10 - 30% | 25 - 50% |
| AREA | 1x | O.6x - 0.4x |
| ACTIVE PWR | 1x | ~0.8x |
| LKG PWR | 1x | 0.7x - 0.5x |
| PERFORMANCE | 1x | 1x |
Note: Small-range register files are highly un-optimized due to a large Periphery logic overhead
Sub-0.3v NTST (Near-Threshold & Sub-Threshold) Register File < 16Kb
| Competition | Hhigh Circuits | |
|---|---|---|
| Bitcell | No offering | Logic Bitcell |
| ACTIVE PWR | No offering | Ultra Low |
| LKG PWR | No offering | Same as ULL |
| PERFORMANCE | No offering | Same as Logic |
Note: NTST Register Files are required for AIML and IoT to improve energy efficiency further upto MEP limit
Multiport Register File upto 6-port
| Competition | Hhigh Circuits | |
|---|---|---|
| 1R1W | Offers | Offers 30% - 50% Lower Power |
| Dual Port | Offers | Offers 30% - 50% Lower Power |
| 2R1W, 2R2W, 3R2W, 3R3W etc. | No offering | Offers with highly optimized PPA |
Note: Multiport register files are a MUST for high-throughput AIML applications and high-performance compute
Special Custom Memory Solutions
| Competition | Hhigh Circuits | |
|---|---|---|
| TCAM, Pseudo - Port, ROM | Offers | 30% - 50% Lower Power |
| Single - Supply Register File | No offering | Offers with highly optimized PPA |
| Sequential Access Register File | No offering | Offers with highly optimized PPA |
| Synthesizable Register File | No offering | Offers with highly optimized PPA |
Note: The need for new kinds of memories and solutions is being felt as new algorithms and architectures evolve in AIML and IoT