Customer Engagement
Current Customer engagements – Tier-1 Fabless Semi Company & Tier-1 Fab
Pre-Silicon engagement in T&M Services and future engagement on the lines of Licensing to be mutually discussed post-Silicon
Have entered into an agreement for cache memory power optimization
Silicon data expected during second half of 2024
Near Term Pre-Silicon Engagement in T&M Services addressing In-house Memory Design Team
Long Term Engagement on the lines of Licensing to be discussed post successful Silicon results
Extension of silicon proven innovative design to other instances or to the compiler
Business engagement model justifying the pre-silicon engagement
Customer to get early access to innovated technology while Hhigh Circuits gets an opportunity to work with a Lead Customer
Flexible on Engagement model
Exact engagement model with an attractive RoI for the customer to be mutually aligned
Memory Solutions for AIML & IoT
ULP and ULL SRAM < 1Mb
| Competition | Hhigh Circuits | |
|---|---|---|
| AREA | 1x | 1x |
| ACTIVE PWR | 1x | 0.7x - 0.5x |
| LKG PWR | 1x | 0.7x - 0.5x |
| PERFORMANCE | 1x | 1x |
Note: Large-range SRAMs are reqd. to implement L2 and L3 Caches and to store on-chip Input and Filter data in AIML. Both active and leakage power are critical
0.5v-0.4v ULV SRAM < 512Kb
| Competition | Hhigh Circuits | |
|---|---|---|
| AREA | 1x | 1x |
| ACTIVE PWR | 1x | 0.5x |
| LKG PWR | 1x | 0.5x |
| PERFORMANCE | 1x | 1x |
Note: ULV SRAMs are required for AIML and IoT applications to improve energy efficiency drastically
Small-range Single and Two Port RF < 16Kb
| Competition | Hhigh Circuits | |
|---|---|---|
| Array Efficiency | 10 - 30% | 25 - 50% |
| AREA | 1x | O.6x - 0.4x |
| ACTIVE PWR | 1x | ~0.8x |
| LKG PWR | 1x | 0.7x - 0.5x |
| PERFORMANCE | 1x | 1x |
Note: Small-range register files are highly un-optimized due to a large Periphery logic overhead
Sub-0.3v NTST (Near-Threshold & Sub-Threshold) Register File < 16Kb
| Competition | Hhigh Circuits | |
|---|---|---|
| Bitcell | No offering | Logic Bitcell |
| ACTIVE PWR | No offering | Ultra Low |
| LKG PWR | No offering | Same as ULL |
| PERFORMANCE | No offering | Same as Logic |
Note: NTST Register Files are required for AIML and IoT to improve energy efficiency further upto MEP limit
Multiport Register File upto 6-port
| Competition | Hhigh Circuits | |
|---|---|---|
| 1R1W | Offers | Offers 30% - 50% Lower Power |
| Dual Port | Offers | Offers 30% - 50% Lower Power |
| 2R1W, 2R2W, 3R2W, 3R3W etc. | No offering | Offers with highly optimized PPA |
Note: Multiport register files are a MUST for high-throughput AIML applications and high-performance compute
Special Custom Memory Solutions
| Competition | Hhigh Circuits | |
|---|---|---|
| TCAM, Pseudo - Port, ROM | Offers | 30% - 50% Lower Power |
| Single - Supply Register File | No offering | Offers with highly optimized PPA |
| Sequential Access Register File | No offering | Offers with highly optimized PPA |
| Synthesizable Register File | No offering | Offers with highly optimized PPA |
Note: The need for new kinds of memories and solutions is being felt as new algorithms and architectures evolve in AIML and IoT